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DIGITAL ELECTRONICS: LOGIC AND CLOCKS
LAB 9 INTRO: INTRODUCTION TO DISCRETE DIGITAL LOGIC, MEMORY, AND CLOCKS
GOALS
In this experiment, we will learn about the most basic elements of digital electronics, from which more
complex circuits, including computers, can be constructed.
Proficiency with new equipment and approaches:
o
o
Logic gates, memory circuits, digital clocks
Combining components & Boolean logic
DEFINITIONS
Duty cycle – percentage of time during one cycle that a system is active (+5V in the case of digital logic)
Truth table – table that shows all possible input combinations and the resulting outputs of digital logic components
Flip-flop - a circuit that has two stable states and can be used to store state information.
Logic gates – a physical device that implements some Boolean logic operation
DIGITAL CIRCUITS - GENERAL
In almost all experiments in the physical sciences, the signals that represent physical quantities start out as
analog waveforms. To display and analyze the information contained in these signals, they most often are converted
into
digital
data. Often this is done inside a commercial instrument such as an oscilloscope or a lock-in amplifier,
which is then connected to a computer through a digital interface. In other cases, data acquisition cards are added to
a computer chassis, allowing analog signals to be input directly to the computer. Scientists usually buy their data
acquisition equipment rather than build it, so they usually don’t have to know too much about the digital circuitry
that makes it work. Almost all data are eventually analyzed digitally with a computer.
Analog information can be translated into digital form by a device called an Analog-to-Digital Converter (A/D
N
converter or ADC). A set of N bits has 2 possible different values, as you might recall from Lab #5. If you try to
7
represent an analog voltage by 7 bits, your minimum uncertainty will be about 1%, since there are 2 = 128 possible
combinations of 7 bits. For higher accuracy you need more bits. The corresponding device that can convert digital
data back into an analog waveform is called a Digital-to-Analog Converter (D/A converter or DAC), which we built in
Lab #5.
Logic gates alone can be used to construct arbitrary combinatorial logic (they can generate any truth-table),
but to create a machine that steps through a sequence of instructions like a computer does, we also need memory
and a clock. The fundamental single-bit memory element of digital electronics is called a flip-flop. We will study two
types, called SR (or RS) and JK. The flip-flops we have chosen are from the TTL (Transistor-transistor logic) family. A
digital clock
is a repeating digital waveform used to step a digital circuit through a sequence of states. We will
introduce the 555 timer chip and use it to generate a clock signal. Digital circuits that are able to step through a
sequence of states with the aid of flip-flops and a clock are called sequential logic.
1
DIGITAL LOGIC STATES
The voltage in a digital circuit is allowed to be in only one of two states: HIGH or LOW. HIGH is taken to mean
logical (1) or logical TRUE. LOW is taken to mean logical (0) or logical FALSE. In the TTL logic family (see Figure 1), the
“ideal” HIGH and LOW voltage levels are 5 V and 0 V but any input voltage in the range 2 to 5.0 V is interpreted as
HIGH, and any input voltage in the range 0 to 0.8 V as LOW. Voltages outside this range are undefined, and therefore
“illegal,” except if they occur briefly during transitions. If the input to a TTL circuit is a voltage in this undefined range,
the response is unpredictable, with the circuit sometimes interpreting it as a “1” and sometimes as a “0.” Avoid
sending voltage in the undefined range into a TTL components.
Figure 1: TTL Input Voltage Levels
DIGITAL LOGIC GATES
The flow of digital signals is controlled by transistors in various configurations depending on the logic family
(see H&H 8.09 for details). For most purposes, we can imagine that the logic gates are composed of several ideal
switches with just two states: OPEN and CLOSED. The state of a switch is controlled by a digital signal. The switch
remains closed so long as a logical (1) signal is applied. A logical (0) control signal keeps it open.
Logic signals interact by means of gates. The three fundamental gates, AND, OR, and NOT, are named after
the three fundamental operations of logic that they carry out. The AND and OR gates each have two inputs and one
output. The output state is determined by the states of the two inputs. The NOT gate has one input and one output.
The function of each gate is defined by a truth table, which specifies the output state for every possible
combination of input states. The output values of the truth tables can be understood in terms of two switches. If the
switches are in series, you get the AND function. Parallel switches perform the OR operation. The most common gates
are shown in Fig. 2. A small circle after a gate or at an input on the schematic symbol indicates negation (NOT).
2
Operation
Switches
Condition that
circuit is closed
AND
Boolean
Notation
Symbol
Truth Table
A
Series
B
(A AND B are closed)
A• B
A
B
A
.
B
A B
0 0
0 1
1
0
1 1
A B
A
.
B
0
0
0
1
A+B
OR
A
B
Parallel
(A OR B is closed)
A
+
B
A
B
A+B
0
0
1
1
0
1
0
1
0
1
1
1
NOT
(same as
invert)
Different
kind of switch
1 means open
0 means closed
NOT (
A
)
≡
A
A
_
A
A
_
A
1
0
0
1
Compound Gates
NAND
A
B
A
.
B
NOR
XOR
A
B
A
B
A+B
A+B
=AB+AB
Figure 2: Digital Logic gates
3
MEMORY ELEMENTS AND FLIP-FLOPS
In sequential logic circuits, the output depends upon previous values of the input signals as well as their
present-time values. Such circuits necessarily include memory elements that store the logic values of the earlier
signals. The fundamental memory circuit is the RS memory element. The JK flip-flop has an RS flip-flop at its core, but
it adds circuitry that synchronizes output transitions to a clock signal. Timing control by a clock is essential to most
complex sequential circuits
RS Memory Circuit
The truth table for the RS memory element shows how the circuit remembers. Suppose that it is originally in a state
with Q=0 and R=S=0. A positive pulse S at the input sets it into the state Q=1, where it remains after S returns to zero.
A later pulse R on the other input resets the circuit to Q=0, where it remains until the next S pulse.
RS MEMORY
Signals
R
S
Q
SET
RESET
time
Circuit
R
Q = R+ P
R
S
Symbol
Q
Q
S
0
1
0
1
Truth Table
R Q P= Q
0 Stays the same
0
0 1
1
1 0
0 P= Q
1 0
Disallowed
S
P= S + Q
Figure 3: RS memory element.
JK Flip-Flop (TTL74107)
There are three kinds of inputs to the JK flip-flop
1) data inputs J and K
2) the clock C
3) the direct input CLR (clear)
There are two outputs: Q and its compliment.
Figure 4: JK Flip-Flop
n counts the number of clock pulses since the start of the experiment. In the absence of a clock pulse, the output
remains unchanged at the previously acquired value, Q
n
, which is independent of the present-time data inputs J and K.
Only on the arrival of a clock pulse, C, can the output change to a new value, Q
n+1
. The value of Q
n
depends on the J
and K inputs in the way specified in the truth table. The change occurs at the falling (trailing) edge of the clock pulse,
indicated by a downward arrow in the truth table in Fig. 4.
The direct input, CLR, overrides the clock and data inputs. During normal operation, CLR = 1. At the moment CLR goes
to zero, the output goes to zero and remains there as long as CLR = 0.
4
555 Timer and Digital Clock
See FC section 11.14 for a description of the guts of the 555 timer chip. Figure 9.7 shows the circuit for generating a
clock with the 555 and summarizes the formulas relating the resistor and capacitor values to the output low time T1
and the output high time T2
(a) Astable circuit (Digital Clock)
+5V
1
GND
+
555
8
7
6
5
RA
RB
VC
Output
2
TRIG
3
OUT
4
RST
DIS
THR
BYP
(b) Component values
Output High (charge time):
T2 = (RA+RB)C ln2
Output Low (discharge):
T1 = RBC ln2
Period: T = T1 + T2
(c) Limiting Values
Max RA, RB 3.3 MΩ
Min RA, RB 1 kΩ
Min. C 500pf
0.1uf
C
0V
(d) Voltage outputs
Pin 6 - Capacitor Voltage V c
Supply Voltage (5V)
Threshold Level
Trigger Level
time
t2
DC Volts
V+
t1
Pin 3
Output Voltage
C charges through RA and RB in series
C discharges through RB only
Output is positive while C is charging
Output is grounded while C is discharging
DC Volts
V+
.667 V+
.333 V+
time
Figure 9.7 Astable circuit using 5 55 Timer chip
5

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