TDA8044.PDF

(101 KB) Pobierz
INTEGRATED CIRCUITS
DATA SHEET
TDA8044
Satellite demodulator and decoder
Product specification
Supersedes data of 1998 Nov 17
File under Integrated Circuits, IC02
2000 Feb 21
Philips Semiconductors
Product specification
Satellite demodulator and decoder
FEATURES
•
General features:
– One-chip Digital Video Broadcasting (DVB)
compliant Quadrature Phase Shift Keying (QPSK)
and Binary Phase Shift Keying (BPSK) demodulator
and concatenated Viterbi/Reed-Solomon decoder
with de-interleaver and de-randomizer
(ETS 300 421)
– 3.3 V supply voltage (input pads are 5 V tolerant)
– Standby mode for low power dissipation
– Internal clock PLL to allow low frequency crystal
application and selectable clock frequencies
– Power-on reset module
– Package: QFP100
– Boundary scan test.
•
QPSK/BPSK demodulator:
– Interpolator and anti-alias filter to handle a large
range of symbol rates without additional external
filtering
– On-chip AGC of the analog input I and Q baseband
signals or tuner AGC control
– Two on-chip matched Analog-to-Digital Converters
(ADCs; 7 bits)
– Half Nyquist (square root raised-cosine) filter with
selectable roll-off factor
– Large range of symbol frequencies:
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
Single Carrier Per Channel (SCPC) function
– Can be used at low channel Signal-to-Noise ratio
(S/N)
– Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters
– Two loop carrier recovery enabling phase tracking of
the incoming symbols
– Software carrier sweep for low symbol rate
applications
– Signal-to-noise ratio estimation
– External indication of demodulator lock.
•
Viterbi decoder:
– Rate
1
⁄
2
convolutional code based
– Constraint length K = 7 with G
1
= 171
oct
and
G
2
= 133
oct
; supported puncturing code rates:
1
⁄
,
2
⁄
,
3
⁄
,
4
⁄
,
5
⁄
,
6
⁄
,
7
⁄
and
8
⁄
2
3
4
5
6
7
8
9
– 4 bits input for ‘soft decision’ for both I and Q
2000 Feb 21
2
TDA8044
– Truncation length: 144
– Automatic synchronization
– Channel Bit Error Rate (BER) estimation
– External indication of Viterbi sync lock
– Differential decoding optional.
•
Reed-Solomon (RS) decoder:
– (204, 188, T = 8) Reed-Solomon code
– Automatic (I
2
C-bus configurable) synchronization of
bytes, transport packets and frames
– Internal convolutional de-interleaving (I = 12; using
internal memory)
– De-randomizer based on Pseudo Random Bit
Sequence (PRBS)
– External indication of Register Select (RS) decoder
sync lock
– External indication of uncorrectable error (transport
error indicator is set)
– External indication of corrected byte
– Indication of the number of lost blocks
– Indication of the number of corrected blocks.
•
Interface:
– I
2
C-bus interface to initialize and monitor the
demodulator and Forward Error Correction (FEC)
decoder; when no I
2
C-bus usage, default mode is
defined
– Programmable interrupt facility
– 6 bits I/O expander for flexible access to and from the
I
2
C-bus
– Switchable I
2
C-bus loop-through to suppress I
2
C-bus
crosstalk in the tuner
– DiSEqC level 1.X support for dish control applications
– 3-state mode for transport stream outputs.
APPLICATIONS
•
Digital satellite TV: demodulation and Forward Error
Correction (FEC).
Philips Semiconductors
Product specification
Satellite demodulator and decoder
GENERAL DESCRIPTION
This document gives preliminary information about the
TDA8044 and TDA8044A, which are the successors of the
TDA8043. The TDA8044A is only specified where the
product deviates from the TDA8044, all other references
are the same. The TDA8044 is backwards compatible with
the TDA8043, with respect to pinning and the I
2
C-bus
software. The TDA8044 is a DVB compliant demodulator
and error correction decoder IC for reception of QPSK and
BPSK modulated signals for satellite applications. It can
handle variable symbol rates in the range of
0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for
TDA8044A) with a minimum number of low cost and
non-critical external components. Typical applications for
this device are Multi Channel Per Carrier (MCPC), Single
Channel Per Carrier (SCPC) and simulcast. In these
applications one satellite transponder contains
respectively one broad QPSK carrier, several small QPSK
carriers and one small QPSK carrier together with one or
two FM carriers.
The TDA8044 has minimum interface with the tuner, it only
requires the demodulated analog I and Q baseband input
signals. Analog-to-digital conversion is performed
internally by two matched 7-bit ADCs. Since all the loops
(AGC, clock and carrier recovery) are internal, no
feedback to the tuner is needed. However, for maximum
tuner flexibility, there is the possibility to close the AGC
and carrier recovery loop externally via the tuner.
The number of external components required for operation
of the TDA8044 is very low. Moreover the external
components are low cost and non-critical. This gives an
easy and low cost application. The TDA8044 operates on
a low frequency crystal which is upconverted to a clock
frequency by means of an internal PLL. Different clock
frequencies can be selected with the PLL without changing
the crystal. This allows for maximum flexibility concerning
symbol rate range combined with minimum power
consumption.
TDA8044
The TDA8044 also has internal anti-alias filters, which can
cover a large range of symbol frequencies (approximately
one decade) without the need to switch external (SAW)
filters. To cover the whole range of 0.5 to 45 Msymbols/s
switching of clock frequency (internally) and filtering
(externally) is necessary.
The TDA8044 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely
internally, thereby minimizing I
2
C-bus communication.
The output of the TDA8044 is highly flexible, allowing
different output modes to interface to a
demultiplexer/descrambler/MPEG-2 decoder including a
3-state mode. For evaluation of the TDA8044,
demodulator and Viterbi outputs can be made available
externally.
Interfacing to the TDA8044 has been extended compared
to the TDA8043. Separate resets are available for logic
only, logic plus I
2
C-bus and carrier loops. A Power-on
reset module has been implemented which gives a reset
signal at power-up. This signal can be used to reset the
TDA8044 in order to guarantee correct starting of the IC.
Two extra general purpose I/O pins (I/O expanders) have
been added. A switchable I
2
C-bus loop-through to the
tuner is implemented to switch-off the I
2
C-bus connection
to the tuner. This reduces phase noise in the tuner in the
event of I
2
C-bus crosstalk. The transport stream outputs
can be put in 3-state mode. DiSEqC level 1.X support is
integrated for dish control applications. The power
consumption in standby mode has been decreased
considerably.
2000 Feb 21
3
Philips Semiconductors
Product specification
Satellite demodulator and decoder
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DD(tot)
PARAMETER
analog supply voltage
digital supply voltage
total supply current
TDA8044
TDA8044A
f
clk
internal clock frequency
TDA8044
TDA8044A
r
s
symbol rate
TDA8044
TDA8044A
P
tot
total power dissipation
TDA8044
TDA8044A
IL
S/N
Notes
1. Programmable internal frequencies possible:
a) Values 10.7, 16, 32 or 64 MHz for CFS = 0.
b) Values 16, 24, 48 or 96 MHz for CFS = 1.
2. CFS is set to logic 0.
implementation loss
signal-to-noise ratio for locking
the TDA8044
note 5
note 5
T
amb
= 70
°C;
note 4
−
−
−
2
1150
−
0.3
−
V
DDD
= 3.3 V
note 1
notes 1 and 2
CFS = 0 or CFS = 1;
f
xtal
= 4 MHz
note 1
notes 1 and 2
note 3
0.5
0.5
−
−
45
30
10.7
10.7
−
−
96
64
−
−
320
−
480
350
CONDITIONS
MIN.
3.05
3.05
TYP.
3.3
3.3
TDA8044
MAX.
3.55
3.55
V
V
mA
mA
UNIT
MHz
MHz
Msymbols/s
Msymbols/s
mW
mW
dB
dB
1700
1250
−
−
3. Without switching internal clock frequencies, a range of 1 decade can be covered. To cover the full range of symbol
frequencies, internal clock frequencies and external (SAW) filters must be switched. Details can be found in the
application note.
4. Maximum value is specified for a symbol rate of 45 Msymbols/s, a puncturing rate of
7
⁄
8
, a clock frequency of 96 MHz
and a 3.55 V power supply. The typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of
3
⁄
4
and a clock frequency of 64 MHz.
5. Implementation loss at the demodulator output and minimum S/N to lock the TDA8044 are measured including tuner
in a laboratory environment at a symbol rate of 27.5 Msymbols/s and a clock frequency of 64 MHz.
ORDERING INFORMATION
TYPE
NUMBER
TDA8044H
TDA8044AH
PACKAGE
NAME
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
VERSION
SOT317-2
2000 Feb 21
4
Philips Semiconductors
Product specification
Satellite demodulator and decoder
PINNING
SYMBOL
I2
I3
V
SSD1
CFS
V
SSD2
I4
I5
I6
Q0
V
DDD1
Q1
Q2
Q3
Q4
V
SSD3
Q5
Q6
V
SSD4
V
DDD2
PRESET
P3
P2
P1
P0
V
DDD3
P5
P4
PDOCLK
PDO0
PDO1
PDO2
V
SSD5
PDO3
PDO4
PDO5
V
SSD6
V
SSD7
PDO6
POR
V
DDD4
2000 Feb 21
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
I
I
−
I
−
I
I
I
I
−
I
I
I
I
−
I
I
−
−
I
I/O
I/O
I/O
I/O
−
I/O
I/O
O
O
O
O
−
O
O
O
−
−
O
I
−
DESCRIPTION
digital I-input bit 2 (ADC bypass)
digital I-input bit 3 (ADC bypass)
digital ground 1
clock frequency selection (remains at logic 0 for TDA8044A)
digital ground 2
digital I-input bit 4 (ADC bypass)
digital I-input bit 5 (ADC bypass)
digital I-input bit 6 (ADC bypass: MSB)
digital Q-input bit 0 (ADC bypass: LSB)
digital supply voltage 1
digital Q-input bit 1 (ADC bypass)
digital Q-input bit 2 (ADC bypass)
digital Q-input bit 3 (ADC bypass)
digital Q-input bit 4 (ADC bypass)
digital ground 3
digital Q-input bit 5 (ADC bypass)
digital Q-input bit 6 (ADC bypass: MSB)
digital ground 4
digital supply voltage 2
set device into default mode
quasi-bidirectional I/O port (bit 3)
quasi-bidirectional I/O port (bit 2)
quasi-bidirectional I/O port (bit 1)
quasi-bidirectional I/O port (bit 0)
digital supply voltage 3
quasi-bidirectional I/O port (bit 5)
quasi-bidirectional I/O port (bit 4)
output clock for transport stream bytes
parallel data output (bit 0)
parallel data output (bit 1)
parallel data output (bit 2)
digital ground 5
parallel data output (bit 3)
parallel data output (bit 4)
parallel data output (bit 5)
digital ground 6
digital ground 7
parallel data output (bit 6)
Power-on reset [can be connected to PRESET (pin 20)]
digital supply voltage 4
5
TDA8044

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin