MC68000_16-Bit_Microprocessor_Data.pdf

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MC68000
16-BIT
MICROPROCESSOR
APRIL, 1983
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
©MOTOROLA INC., 1983
ADI-814-R4
Motorola reserves the right to make changes to any products herein to improve reliability. function or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
Section 1
Introdu ction
1.1
1.2
Data Types and Addressing Modes.....................................................
Instruction Set Overview..................................................................
Section 2
Data Organization and Addressing Capabilities
1-1
1-3
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.1.1
2.8.1.2
2.8.2
2.8.2.1
2.8.2.2
2.8.2.3
2.8.2.4
2.8.2.5
2.8.3
2.8.3.1
2.8.3.2
2.8.3.3
2.8.3.4
2.8.3.5
2.8.3.6
2.9
2.10
Operand Size................................................................................
Data Organization in Registers...........................................................
Data Registers.........................................................................
Address Registers....................................................................
Data Organization in Memory............................................................
Addressing...................................................................................
Instruction Format..........................................................................
Program/ Data References................................................................
Register Specification.....................................................................
Effective Address.. .. .. . . . .. .. . .. ... . . .. . ... ..... .... ... .. . .. . . . . . . .. ... ... ... ... . ... . . .. . ..
Register Direct Modes...............................................................
Data Register Direct............................................................
Address Register Direct.......................................................
Memory Address Modes............................................................
Address Register Indirect.....................................................
Address Register Indirect with Postincrement............................
Address Register Indirect with Predecrement ............................
Address Register Indirect with Displacement.............................
Address Register Indirect with Index.......................................
Special Address Modes.............................................................
Absolute Short Address....... .... ....... ... .... ..... ................ ... ......
Absolute Long Address.. ... . ... . ... . . .. . . . . .. . .. . . . .. ... ... . . . ... ... . ... .....
Program Counter with Displacement.......................................
Program Counter with Index.................................................
Immediate Data.................................................................
Implicit Reference..............................................................
Effective Address Encoding Summary.................................................
System Stack................................................................................
2-1
2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-4
2-4
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-6
2-6
2-6
2-6
2-6
iii
TABLE OF CONTENTS
(Continued)
Paragraph
Number
Title
Section 3
Instruction Set Summary
3.1
3.2.
3.3
3.4
3.5
3.6
3.7
3.8
Data Movement Operations..............................................................
Integer Arithmetic Operations............................................................
logical Operations..........................................................................
Shift and Rotate Operations ................... '" ........... .................. ..... ... ...
Bit Manipulation Operations..............................................................
Binary Coded Decimal Operations......................................................
Program Control Operations.............................................................
System Control Operations....................................... ....... ....... ..........
3-1
3-2
3-3
3-3
3-4
3-4
3-4
3-5
Page
Number
Section 4
Signal and Bus Operation Description
4.1
4.1.1
4.1.2
4.1.3
4.1.3.1
4.1.3.2
4.1.3.3
4.1.3.4
4.1.4
4.1.4.1
4.1.4.2
4.1.4.3
4.1.5
4.1.6
4.1.6.1
4.1.6.2
4.1.6.3
4.1.7
4.1.7.1
4.1.7.2
4.1.7.3
4.1.8
4.1.9
4.1.10
4.2
4.2.1
4.2.1.1
Signal Description..........................................................................
Address Bus (A 1 through A23) ....................................................
Data Bus (DO through D15).........................................................
Asynchronous Bus Control.........................................................
Address Strobe (AS)...........................................................
Read/Write (R/W) .............................................................
Upper and lower Data Strobe (UDS, lDS)................... ............
Data Transfer Acknolwedge (DTACK) .....................................
Bus Arbitration Control..............................................................
Bus Request (BR)............................ ...... ........ ...... ...............
Bus Grant (BG) ....................... '" ............. ... ......... ... .... ........
Bus Grant Acknowledge (BGACK) .........................................
Interrupt Control (lPlO, IPl1, IPl2)...............................................
System Control .................. '" ........ '" . ... . . . . . ... . . .. .. .... ... .. .. ..... . . ... .
Bus Error (BERR) ......................................... ....... ........ .......
Reset (RESET)...................................................................
Halt (HALT) ......................................................................
M6800 Peripheral Control...........................................................
Enable (E) .......... " .................................. , . ..... ..... .... . ... . .... . .
Valid Peripheral Address (VPA) ..............................................
Valid Memory Address (VMA) ...............................................
Processor Status (FCO, FC1, FC2) ................................................
Clock (ClK) ............ .................... ........ ...... ... ... ........ ... ...... .... ...
Signal Summary......................................................................
Bus Operation...............................................................................
Data Transfer Operations........................... ................................
Read Cycle............. ............................. . ............................
4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-4
4-4
4-5
4-5
4-5
4-5
4-6
iv
TABLE OF CONTENTS
(Continued)
Paragraph
Number
Page
Number
Title
4.2.1.2
4.2.1.3
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.5
4.3
4.4
4.4.1
4.4.2
Write Cycle... ...... .... ... ............ ..... ... .... ........ .............. .........
Read-Modify-Write Cycle .....................................................
Bus Arbitration........................................................................
Requesting the Bus .............................................................
Receiving the Bus Grant .......................................................
Acknowledgement of Mastership ...........................................
Bus Arbitration Control..............................................................
Bus Error and Halt Operation.......................................................
Bus Error Operation............................................................
Re-Run Operation ..............................................................
Halt Operation ...................................................................
Double Bus Faults..............................................................
Reset Operation.......................................................................
The Relationship of DTACK, BERR, and HALT ......................................
Asynchronous versus Synchronous Operation .......................................
Asynchronous Operation...........................................................
Synchronous Operation .............................................................
Section 5
Processing States
4-8
4-10
4-11
4-13
4-13
4-13
4-14
4-14
4-18
4-18
4-19
4-20
4-20
4-21
4-23
4-23
4-23
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
Privilege States..............................................................................
Supervisor State......................................................................
User State..............................................................................
Privilege State Changes... .. ..... ........... ..... . . .............. ...... ....... ... ...
Reference Classification.............................................................
Exception Processing......................................................................
Exception Vectors....................................................................
Kinds of Exceptions..................................................................
Exception Processing Sequence...................................................
Multiple Exceptions.............................................. ....................
Exception Processing Detailed Discussion............................................
Reset ...... .... ... .............. .... ... ... .......... ........ ... ..................... .....
Interrupts............. ........................ ..........................................
Uninitialized Interrupt................................................................
Spurious Interrupt....................................................................
Instruction Traps......................................................................
Illegal and Unimplemented Instructions..........................................
Privilege Violations................. ................................. .............. . ..
Tracing ..................................................................................
Bus Error ................................................................................
Address Error ....................................................... ,. .................
5-1
5-2
5-2
5-2
5-2
5-3
5-3
5-4
5-5
5-5
5-6
5-6
5-7
5-9
5-9
5-9
5-9
5-10
5-10
5-10
5-11
v

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