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Chapter 2
Clocks and Resets
2.1
Introduction
The cost of designing ASICs is increasing every year. In addition to the non-recurring
engineering (NRE) and mask costs, development costs are increasing due to ASIC
design complexity. To overcome the risk of re-spins, high NRE costs, and to
reduce time-to-market delays, it has become very important to design the first time
working silicon.
This chapter constitutes a general set of recommendations intended for use by
designers while designing a block or an IP (Intellectual Property). The guidelines
are independent of any CAD tool or silicon process and are applicable to any ASIC
designs and can help designers to plan and to execute a successful System on Chip
(SoC) with a well-structured and synthesizable RTL code.
The current paradigm shift towards system level integration (SLI), incorporating
multiple complex functional blocks and a variety of memories on a single circuit,
gives rise to a new set of design requirements at integration level. The recommenda-
tions are principally aimed at the design of the blocks and memory interfaces which
are to be integrated into the system-on-chip. However, the guidelines given here are
fully consistent with the requirements of system level integration and will signifi-
cantly ease the integration effort, and ensure that the individual blocks are easily
reusable in other systems.
These guidelines can form as a basis of checklist that can be used as a signoff for
each design prior to submission for fabrication.
2.2
Synchronous Designs
Synchronous designs are characterized by a single master clock and a single master
set/reset driving all sequential elements in the design.
M. Arora,
The Art of Hardware Architecture: Design Methods and Techniques
for Digital Circuits,
DOI 10.1007/978-1-4614-0397-5_2,
© Springer Science+Business Media, LLC 2012
11
12
q1
q2
2 Clocks and Resets
q3
D
Q
D
Q
D
Q
CK
CK
CK
q1
q2
q3
cumulative delay
Fig. 2.1
Flip flop driving the clock input of another flip flop (ripple counter)
Experience has shown that the safest methodology for time domain control of an
ASIC is synchronous design. Some of the problems with the circuits not being syn-
chronous have been shown in this section.
2.2.1
Avoid Using Ripple Counters
Flip Flops driving the clock input of other flip flops is somewhat problematic. The
clock input of the second flip-flop is skewed by the
clock-to-q
delay of the first flip-
flop, and is not activated on every clock edge. This cumulative effect with more than
two Flip Flops connected in a similar manner forms a Ripple counter as shown in
Fig.
2.1.
Note the cumulative delay gets added on with more number of flip flops
and hence the same is not recommended. More details on the ripple counter are
given in Sect. 5.6.7.
2.2.2
Gated Clocks
Gating in a clock line causes clock skew and can introduce spikes which trigger the
flip-flop. This is particularly the case when there is a multiplexer in the clock line as
shown in Fig.
2.2.
Simulating a gated clock design might work perfectly fine but the problem arises
when such a design is synthesized.
2.2
Synchronous Designs
q1
13
D
EN
CLK
CK
Q
Fig. 2.2
Gated clock line
D
Q
D
Q
CK
CK
CLK
Fig. 2.3
Double-edged clocking
2.2.3
Double-Edged or Mixed Edge Clocking
As shown in Fig.
2.3,
the two flip-flops are clocked on opposite edges of the
clock signal. This makes synchronous resetting and test methodologies such as
scan-path insertion difficult, and causes difficulties in determining critical signal
paths.
2.2.4
Flip Flops Driving Asynchronous Reset of Another Flop
In Fig.
2.4,
the second flip-flop can change state at a time other than the active clock
edge, violating the principle of synchronous design. In addition, this circuit contains
a potential race condition between the clock and reset of the second flip-flop.
The subsequent sections show the methods to avoid the above non-recommended
circuits.
14
2 Clocks and Resets
D
Q
D
Q
CK
CK
CLR
CLK
Fig. 2.4
Flip flop driving asynchronous reset of another flop
2.3
Recommended Design Techniques
When designing with HDL code, it is important to understand how a synthesis tool
interprets different HDL coding styles and the results to expect. It is very important
to think in terms of hardware as a particular design style (or rather coding style) can
affect gate count and timing performance. This section discusses some of the basic
techniques to ensure optimal synthesis results while avoiding several causes of
unreliability and instability.
2.3.1
Avoid Combinational Loops in Design
Combinational loops are among the most common causes of instability and unreli-
ability in digital designs. In a synchronous design, all feedback loops should include
registers. Combinational loops violate synchronous design principles by establish-
ing a direct feedback with no registers.
In terms of HDL language, combinational loops occur when the generation of a
signal depends on itself through several combinational
always
1
blocks or when the
left-hand side of an arithmetic expression also appears on the right-hand side.
Combo loops are a hazard to a design and synthesis tools will always give errors
when combo loops are encountered, as these are not synthesize-able.
The generation of combo loops can be understood from the following bubble
diagram in Fig.
2.5.
Each bubble represents a combo always block and the arrow
going into it represents the signal being used in that always block while an arrow
going out from the bubble represents the output signal generated by that output
block. It is evident that the generation of signal ‘a’ depends on itself through signal
‘d’, thereby generation a combinational loop.
1
For simplicity, any HDL languages that this book refers to takes Verilog as an example.
2.3 Recommended Design Techniques
15
always@ (a)
begin
b = a;
End
always@ (b)
begin
c = b;
End
always
always@ (c)
begin
d = c;
End
always@ (c)
Begin
a = c;
end
always
a
d
always
b
always
c
Fig. 2.5
Combinational loop example and bubble diagram
D
Q
Logic
CK
CLR
Fig. 2.6
Combinational loop through asynchronous control pins
The code and the bubble diagram are shown below [28]:
In order to remove combo loops, one must change the generation of one of the
signals so the dependency of signals on each other is removed. Simple resolution to
this problem is to introduce a Flip Flop or register in the combo loop to break this
direct path.
Figure
2.6
shows another example where output of a register directly controls the
asynchronous pin of the same register through combinational logic.
Combinational loops are inherently high-risk design structures. Combinational
loop behavior generally depends on the relative propagation delays through the
logic involved in the loop. Propagation delays can change based on various factors
and the behavior of the loop may change. Combinational loops can cause endless

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