ST92195B(1).pdf

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ST92195B
32-64K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
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Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
0°C to +70°C operating temperature range
Up to 24 MHz. operation @ 5V±10%
Min. instruction cycle time: 165ns at 24 MHz.
32, 48, 56 or 64 Kbytes ROM
256 bytes RAM of Register file (accumulators or
index registers)
256 bytes of on-chip static RAM
2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, defin-
able by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
VPS and Wide Screen Signalling slicer (on
some devices)
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference
voltage
Up to 6 external interrupts plus one Non-
Maskable Interrupt
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
16-bit watchdog timer with 8-bit prescaler
One 16-bit standard timer with 8-bit prescaler
4-channel A/D converter; 5-bit guaranteed
PSDIP56
TQFP64
See end of document for ordering information
Rich instruction set and 14 addressing modes
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Versatile
development
tools,
including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
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Pin-compatible EPROM and OTP devices
available
Device Summary
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Device
ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7
ST92T195B7
ST92E195B7
Program
Memory
32K ROM
32K ROM
32K ROM
48K ROM
48K ROM
56K ROM
64K ROM
64K OTP
64K EPROM
TDS VPS/
RAM WSS
2K
6K
6K
6K
8K
8K
8K
8K
8K
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Package
PSDIP56/
TQFP64
CSDIP56
/CQFP64
Rev. 2.5
January 2000
1/22
1
ST92195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92195B microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST92195B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode.
This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode.
The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode.
When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 char-
acter set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
can be used to store Teletext pages as well as Dis-
play parameters.
2/22
ST92195B - GENERAL DESCRIPTION
INTRODUCTION
(Cont’d)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single ex-
ternal crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hard-
ware Hamming decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is out-
put on one of two separate output pins.
1.1.9 PWM Output
Control of TV settings can be made with up to
eight 8-bit PWM outputs, with a maximum frequen-
cy of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency oper-
ation can be programmed.
1.1.10 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single data line for data
input and output. A second line is used for a syn-
chronous clock signal.
1.1.11 Standard Timer (STIM)
The ST92195B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.12 Analog/Digital Converter (ADC)
In addition there is a 4-channel Analog to Digital
Converter with integral sample and hold, fast
5.75µs conversion time and 6-bit guaranteed reso-
lution.
3/22
ST92195B - GENERAL DESCRIPTION
INTRODUCTION
(Cont’d)
Figure 1. ST92195B Block Diagram
Up to 64
Kbytes ROM
256 bytes
RAM
Up to 8
Kbytes TRI
TDSRAM
MEMORY BUS
I/O
PORT 0
8
P0[7:0]
I/O
PORT 2
I/O
PORT 3
I/O
PORT 4
6
P2[5:0]
4
P3[7:4]
256 bytes
Register File
8/16-bit
CPU
8
P4[7:0]
I/O
PORT 5
DATA
SLICER
& ACQUI-
SITIO N
UNIT
SYNC.
EXTRAC-
TION
REGISTER BUS
VPS/WSS
DATA
SLICER
ADC
2
P5[1:0]
NMI
INT[7:4]
INT2
INT0
MMU
Interrupt
Management
ST9+ CORE
TXCF
CVBS1
OSCIN
OSCOUT
RESET
RESETO
RCCU
16-BIT
TIMER/
WATCHDOG
WSCR
WSCF
CVBS2
SDO/SDI
SCK
SPI
AIN[4:1]
EXTRG
VSYNC
HSYNC/CSYNC
CSO
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
MCFM
TIMING AND
CLOCK CTRL
STANDARD
TIMER
SYNC
CONTROL
ON
SCREEN
DISPLAY
PWM
D/A CON-
VERTER
STOUT
VSO[2:1]
VOLTAGE
SYNTHESIS
PWM[7:0]
All alternate functions
(Italic characters)
are mapped on Ports 0, 2, 3, 4 and 5
4/22
ST92195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
Figure 2. 64-Pin Package Pin-Out
V
DD
P0.3
P0.4
P0.5
P0.6
P0.7
RESET
P2.0/INT7
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
V
DD
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDO/SDI/P5.1
INT2/SCK/P5.0
V
DD
JTDO
1
64
48
16
32
V
SS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
N.C. = Not connected
N.C.
N.C.
WSCF
V
PP
/WSCR
AVDD3
TEST0
MCFM
JTCK
TXCF
CVBSO
AVDD2
JTMS
CVBS2
CVBS1
AGND
N.C.
5/22

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