BDL50 LA-D702P.pdf

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B
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E
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Compal Confidential
Diner Braswell M/B LA-D702P Schematics Document
Intel Braswell + ATI R16M-M1-30/70
2015/12/12
Project Code : BDL50
Rev. 0.3 PV
2
3
3
4
4
Security Classification
Compal Secret Data
2015/10/05
Compal Electronics, Inc.
2015/10/05
Title
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Cover Page
Document Number
Thursday, January 07, 2016
Rev
1.0
Sheet
E
Date:
1
of
50
A
B
C
D
E
1
1
2
2
3
3
Sub-borad
page34
CR+USB/B
page34
PWR BTN/B
page36
TP BTN/B
page24
4
4
HDD or SSD/B
page24
Security Classification
Compal Secret Data
2014/07/07
Compal Electronics, Inc.
2015/07/07
Title
ODD/B
A
B
Issued Date
Deciphered Date
Block Diagrams
Rev
1.0
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Thursday, January 07, 2016
2
of
50
C
D
A
B
C
D
E
Voltage Rails
Power Plane
VIN
BATT+
B+
+VSB
1
<PCI-E,SATA,USB3.0>
Description
19V Adapter power supply
12V Battery power supply
AC or battery power rail for power circuit. (19V/12V)
+VSBP to +VSB always on power rail for sequence control
RTC Battery Power
+1.0v Always power rail
+1.2v Always power rail
+1.8v Always power rail
+3.3v Always power rail
+5.0v Always power rail
+1.35V power rail for DDR3L
Core voltage for SOC
GFX voltage for SOC
+0.675V power rail for DDR3L Terminator
+1.0v system power rail
+1.05v system power rail
+1.35v system power rail
+1.5v system power rail
+1.8v system power rail
+3.3v system power rail
+5.0v system power rail
S0
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S4/S5
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
<USB2.0 port>
USB2.0 port
0
1
UMA
USB 3.0 (MB)
USB 2.0 (MB)
Camera
Card Reader
USB 2.0 Hub
Dis
USB 3.0 (MB)
USB 2.0 (MB)
Camera
Card Reader
USB 2.0 Hub
1
DESTINATION
Lane#
USB3.0
0
1
UMA
USB3.0
DIS
USB3.0
+RTCVCC
+1.0VALW
+1.2VALW
+1.8VALW
+3VALW
+5VALW
+1.35V
+SOC_VCC
+SOC_VNN
+0.675VS
+1.0VS
+1.05VS
+1.35VS
+1.5VS
+1.8VS
+3VS
Lane#
SATA
DESTINATION
UMA
HDD
ODD
DIS
HDD
ODD
2
3
4
0
1
Lane#
PCIE
DESTINATION
UMA
DIS
GPU
GPU
WLAN
LAN
<USB2.0 Hub>
USB2.0 port
0
1
2
3
UMA
Touch Screen
USB 2.0 (SB)
BT
Dis
Touch Screen
USB 2.0 (SB)
2
0
1
2
3
WLAN
LAN
2
+5VS
BT
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
4
EC SM Bus1 address
Device
Charger
Battery
BOM Structure Table
BOM Config
@
CONN@
EMI@
@EMI@
ESD@
@ESD@
PX@
8166@
8151@
UMA@
NAT@
AUTO@
TPM@
NTPM@
GCLK@
GCUMA@
GCDIS@
XTAL@
TS@
R30@
R70@
6U@
IND@
Description
Unpop
Connector Part Control by ME
EMI pop component
EMI unpop component
ESD pop component
ESD unpop component
For Discrete Sku
10/100 LAN
Giga LAN
For UMA Sku
EC Non Auto Load Code
EC Auto Load Code
CPU to EC LPC use 3.3V level
CPU to EC LPC use 1.8V level
Pop Green Clock
Pop Green Clock UMA
Pop Green Clock DIS
For XTAL
Pop Touch Screen component
For R16M-M1-30 GPU
For R16M-M1-70 GPU
For 6U@ (Add CRT Component)
Pop for India Sku
4
Address
EC SM Bus2 address
CPU Thermal Sensor
3
4C
UC3
U666
ATI GPU EXO Pro
3
EC SM Bus3 address
GPU Thermal Sensor
4C
UV1
SOC SM Bus address
Device
ChannelA
ChannelB
Touch Pad
Address
A0
A2
DDR DIMM1
DDR DIMM2
4
DAX
ZZZ1
Security Classification
PCB
Part Number = DA6001JC000
PCB LA-C811P REV0 M/B 4
Compal Secret Data
2014/07/07
Compal Electronics, Inc.
2015/07/07
Title
Part Number = RO0000003HM
PCB 102 LA-B151P REV0 M/B 3
45@
HDMI
Issued Date
Deciphered Date
Notes List
Rev
1.0
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Thursday, January 07, 2016
3
of
50
A
B
C
D
5
4
3
2
1
G3->S0
SOC
D
ACIN
+3VLP
EC_ON
+3VALW
+5VALW
SPOK
VNN
+1.05VALW
+1.15VALW
+1.24VALW
+1.8VALW
+3V_SOC
ON/OFF
EC_RSMRST#
PBTN_OUT#
EC_SLP_S4#
-> 2.71ms
110ms
-> 113ms
-> 102.5ms
-> 102.5ms
-> 257.3ms
->
->
571us
4ms
C
0ms
165us
->
->
3.74ms
3.17ms
D
3.69ms
->
->
->
->
->
->
220ms
1.19ms
-840us
2.71ms
16.48ms
19.91ms
27.9ms
C
EC_SLP_S3#
SYSON
+1.35V
DDR_PWROK
VR_ON
+SOC_VGG
+SOC_VCC0/1
VGATE
SUSP#
+1.5VS
+1.8VS
+3VS
B
->
->
->
1.65ms
3.34ms
3.5ms
->
309ms
->
->
3.5ms
3.4ms
->
->
4.77ms
4.97ms
B
+5VS
+0.675VS
not assert
->
8.34ms
KBRST#
PMC_CORE_PWROK
DDR_CORE_PWROK
not assert
PMC_PLTRST#
A
A
Security Classification
Compal Secret Data
2014/08/21
Compal Electronics, Inc.
2015/08/21
Title
Dr-Bios.com
5
4
3
Issued Date
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Power Sequence
Size
C
Date:
Document Number
Thursday, January 07, 2016
1
LA-706P
Rev
0.1
Sheet
4
of
50
5
4
3
2
1
DDR_A_D[0..63]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
USOC1A
CHV_MCP_EDS
DDR0
21
21
21
USOC1B
CHV_MCP_EDS
DDR1
21
DDR_A_MA[0..15]
D
DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0
DDR_A_BS2
DDR_A_BS1
DDR_A_BS0
BD49
BD47
BF44
BF48
BB49
BJ45
BE52
BD44
BE46
BB46
BH48
BD42
BH47
BJ48
BC42
BB47
BF52
AY40
BH46
BG45
BA40
BH44
AU38
AY38
DDR3_M0_MA_15
DDR3_M0_MA_14
DDR3_M0_MA_13
DDR3_M0_MA_12
DDR3_M0_MA_11
DDR3_M0_MA_10
DDR3_M0_MA_9
DDR3_M0_MA_8
DDR3_M0_MA_7
DDR3_M0_MA_6
DDR3_M0_MA_5
DDR3_M0_MA_4
DDR3_M0_MA_3
DDR3_M0_MA_2
DDR3_M0_MA_1
DDR3_M0_MA_0
DDR3_M0_BS_2
DDR3_M0_BS_1
DDR3_M0_BS_0
DDR3_M0_CASB
DDR3_M0_RASB
DDR3_M0_WEB
DDR3_M0_CSB_1
DDR3_M0_CSB_0
DDR3_M0_DQ_63
DDR3_M0_DQ_62
DDR3_M0_DQ_61
DDR3_M0_DQ_60
DDR3_M0_DQ_59
DDR3_M0_DQ_58
DDR3_M0_DQ_57
DDR3_M0_DQ_56
BG33
BH28
BJ29
BG28
BG32
BH34
BG29
BJ33
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
21
21
21
DDR3_M0_DQ_55
DDR3_M0_DQ_54
DDR3_M0_DQ_53
DDR3_M0_DQ_52
DDR3_M0_DQ_51
DDR3_M0_DQ_50
DDR3_M0_DQ_49
DDR3_M0_DQ_48
BD28
BF30
BA34
BD34
BD30
BA32
BC34
BF34
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
BD5
BD7
BF10
BF6
BB5
BJ9
BE2
BD10
BE8
BB8
BH6
BD12
BH7
BJ6
BC12
BB7
BF2
AY14
BH8
BG9
BA14
BH10
AU16
AY16
DDR3_M1_MA_15
DDR3_M1_MA_14
DDR3_M1_MA_13
DDR3_M1_MA_12
DDR3_M1_MA_11
DDR3_M1_MA_10
DDR3_M1_MA_9
DDR3_M1_MA_8
DDR3_M1_MA_7
DDR3_M1_MA_6
DDR3_M1_MA_5
DDR3_M1_MA_4
DDR3_M1_MA_3
DDR3_M1_MA_2
DDR3_M1_MA_1
DDR3_M1_MA_0
DDR3_M1_BS_2
DDR3_M1_BS_1
DDR3_M1_BS_0
DDR3_M1_CASB
DDR3_M1_RASB
DDR3_M1_WEB
DDR3_M1_CSB_1
DDR3_M1_CSB_0
DDR3_M1_DQ_63
DDR3_M1_DQ_62
DDR3_M1_DQ_61
DDR3_M1_DQ_60
DDR3_M1_DQ_59
DDR3_M1_DQ_58
DDR3_M1_DQ_57
DDR3_M1_DQ_56
BG21
BH26
BJ25
BG26
BG22
BH20
BG25
BJ21
D
DDR3_M1_DQ_55
DDR3_M1_DQ_54
DDR3_M1_DQ_53
DDR3_M1_DQ_52
DDR3_M1_DQ_51
DDR3_M1_DQ_50
DDR3_M1_DQ_49
DDR3_M1_DQ_48
BD26
BF24
BA20
BD20
BD24
BA22
BC20
BF20
21 DDR_A_CAS#
21 DDR_A_RAS#
21 DDR_A_WE#
21 DDR_A_CS1#
21 DDR_A_CS0#
21 DDR_A_CLK1
21 DDR_A_CLK1#
21 DDR_A_CKE1
BD38
BF38
AY42
BD40
BF40
BB44
DDR3_M0_DQ_47
DDR3_M0_DQ_46
DDR3_M0_DQ_45
DDR3_M0_DQ_44
DDR3_M0_DQ_43
DDR3_M0_DQ_42
DDR3_M0_DQ_41
DDR3_M0_DQ_40
DDR3_M0_DQ_39
DDR3_M0_DQ_38
DDR3_M0_DQ_37
DDR3_M0_DQ_36
DDR3_M0_DQ_35
DDR3_M0_DQ_34
DDR3_M0_DQ_33
DDR3_M0_DQ_32
AV32
AV34
BD36
BF36
AU32
AU34
BA36
BC36
BH38
BH36
BJ41
BH42
BJ37
BG37
BG43
BG42
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR3_M0_CK_1
DDR3_M0_CKB_1
DDR3_M0_CKE_1
DDR3_M0_CK_0
DDR3_M0_CKB_0
DDR3_M0_CKE_0
21 DDR_A_CLK0
21 DDR_A_CLK0#
21 DDR_A_CKE0
C
AT30
AU30
RSVD1
RSVD2
DDR3_M0_ODT_0
DDR3_M0_ODT_1
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
BD16
BF16
AY12
BD14
BF14
BB10
DDR3_M1_DQ_47
DDR3_M1_DQ_46
DDR3_M1_DQ_45
DDR3_M1_DQ_44
DDR3_M1_DQ_43
DDR3_M1_DQ_42
DDR3_M1_DQ_41
DDR3_M1_DQ_40
DDR3_M1_DQ_39
DDR3_M1_DQ_38
DDR3_M1_DQ_37
DDR3_M1_DQ_36
DDR3_M1_DQ_35
DDR3_M1_DQ_34
DDR3_M1_DQ_33
DDR3_M1_DQ_32
AV22
AV20
BD18
BF18
AU22
AU20
BA18
BC18
BH16
BH18
BJ13
BH12
BJ17
BG17
BG11
BG12
C
DDR3_M1_CK_1
DDR3_M1_CKB_1
DDR3_M1_CKE_1
DDR3_M1_CK_0
DDR3_M1_CKB_0
DDR3_M1_CKE_0
AT24
AU24
AV18
BA16
21
21
DDR_A_ODT0
DDR_A_ODT1
AV36
BA38
+DDRA_SOC_VREFCA
+DDRA_SOC_VREFDQ
AT28
AU28
BA42
AV28
DDR3_M0_OCAVREF
DDR3_M0_ODQVREF
DDR3_M0_DRAMRSTB
DDR3_DRAM_PWROK
21
42
DDR_A_RST#
DDR_PWROK
DDR3_M0_DQ_31
DDR3_M0_DQ_30
DDR3_M0_DQ_29
DDR3_M0_DQ_28
DDR3_M0_DQ_27
DDR3_M0_DQ_26
DDR3_M0_DQ_25
DDR3_M0_DQ_24
BB51
AW53
BC52
AW51
AV51
BC53
AV52
BD52
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
RSVD1
RSVD2
DDR3_M1_ODT_0
DDR3_M1_ODT_1
AT26
AU26
BA12
AV26
DDR3_M1_OCAVREF
DDR3_M1_ODQVREF
DDR3_M1_DRAMRSTB
DDR3_VCCA_PWROK
DDR3_M1_RCOMPPD
DDR3_M1_DM_7
DDR3_M1_DM_6
DDR3_M1_DM_5
DDR3_M1_DM_4
DDR3_M1_DM_3
DDR3_M1_DM_2
DDR3_M1_DM_1
DDR3_M1_DM_0
DDR3_M1_DQ_31
DDR3_M1_DQ_30
DDR3_M1_DQ_29
DDR3_M1_DQ_28
DDR3_M1_DQ_27
DDR3_M1_DQ_26
DDR3_M1_DQ_25
DDR3_M1_DQ_24
BB3
AW1
BC2
AW3
AV3
BC1
AV2
BD2
DDRA_RCOMP
BA28
21
DDR_A_DM[0..7]
DDR3_M0_RCOMPPD
DDR3_M0_DM_7
DDR3_M0_DM_6
DDR3_M0_DM_5
DDR3_M0_DM_4
DDR3_M0_DM_3
DDR3_M0_DM_2
DDR3_M0_DM_1
DDR3_M0_DM_0
DDR3_M0_DQS_7
DDR3_M0_DQSB_7
DDR3_M0_DQS_6
DDR3_M0_DQSB_6
DDR3_M0_DQS_5
DDR3_M0_DQSB_5
DDR3_M0_DQS_4
DDR3_M0_DQSB_4
DDR3_M0_DQS_3
DDR3_M0_DQSB_3
DDR3_M0_DQS_2
DDR3_M0_DQSB_2
DDR3_M0_DQS_1
DDR3_M0_DQSB_1
DDR3_M0_DQS_0
DDR3_M0_DQSB_0
DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
BH30
BD32
AY36
BG41
BA53
AP44
AT48
AP52
DDR3_M0_DQ_23
DDR3_M0_DQ_22
DDR3_M0_DQ_21
DDR3_M0_DQ_20
DDR3_M0_DQ_19
DDR3_M0_DQ_18
DDR3_M0_DQ_17
DDR3_M0_DQ_16
DDR3_M0_DQ_15
DDR3_M0_DQ_14
DDR3_M0_DQ_13
DDR3_M0_DQ_12
DDR3_M0_DQ_11
DDR3_M0_DQ_10
DDR3_M0_DQ_9
DDR3_M0_DQ_8
AV42
AP41
AV41
AT44
AP40
AT38
AP42
AT40
AV45
AY50
AT50
AP47
AV50
AY48
AT47
AP48
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
9
DDR_CORE_PWROK
DDRB_RCOMP
BA26
BH24
BD22
AY18
BG13
BA1
AP10
AT6
AP2
DDR3_M1_DQ_23
DDR3_M1_DQ_22
DDR3_M1_DQ_21
DDR3_M1_DQ_20
DDR3_M1_DQ_19
DDR3_M1_DQ_18
DDR3_M1_DQ_17
DDR3_M1_DQ_16
DDR3_M1_DQ_15
DDR3_M1_DQ_14
DDR3_M1_DQ_13
DDR3_M1_DQ_12
DDR3_M1_DQ_11
DDR3_M1_DQ_10
DDR3_M1_DQ_9
DDR3_M1_DQ_8
AV12
AP13
AV13
AT10
AP14
AT16
AP12
AT14
AV9
AY4
AT4
AP7
AV4
AY6
AT7
AP6
B
DDR_A_DQS7
BH32
DDR_A_DQS#7
BG31
DDR_A_DQS6
BC30
DDR_A_DQS#6
BC32
DDR_A_DQS5
AT32
DDR_A_DQS#5
AT34
DDR_A_DQS4
BH40
DDR_A_DQS#4
BG39
DDR_A_DQS3
AY52
DDR_A_DQS#3
BA51
DDR_A_DQS2
AT42
DDR_A_DQS#2
AT41
DDR_A_DQS1
AV47
DDR_A_DQS#1
AV48
DDR_A_DQS0
AM52
DDR_A_DQS#0
AM51
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR3_M0_DQ_7
DDR3_M0_DQ_6
DDR3_M0_DQ_5
DDR3_M0_DQ_4
DDR3_M0_DQ_3
DDR3_M0_DQ_2
DDR3_M0_DQ_1
DDR3_M0_DQ_0
AP51
AR53
AK52
AL53
AR51
AT52
AL51
AK51
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0
BH22
BG23
BC24
BC22
AT22
AT20
BH14
BG15
AY2
BA3
AT12
AT13
AV7
AV6
AM2
AM3
1 OF 13
BSW-MCP-EDS_FCBGA1170
DDR3_M1_DQS_7
DDR3_M1_DQSB_7
DDR3_M1_DQS_6
DDR3_M1_DQSB_6
DDR3_M1_DQS_5
DDR3_M1_DQSB_5
DDR3_M1_DQS_4
DDR3_M1_DQSB_4
DDR3_M1_DQS_3
DDR3_M1_DQSB_3
DDR3_M1_DQS_2
DDR3_M1_DQSB_2
DDR3_M1_DQS_1
DDR3_M1_DQSB_1
DDR3_M1_DQS_0
DDR3_M1_DQSB_0
DDR3_M1_DQ_7
DDR3_M1_DQ_6
DDR3_M1_DQ_5
DDR3_M1_DQ_4
DDR3_M1_DQ_3
DDR3_M1_DQ_2
DDR3_M1_DQ_1
DDR3_M1_DQ_0
AP3
AR1
AK2
AL1
AR3
AT2
AL3
AK3
B
2 OF 13
BSW-MCP-EDS_FCBGA1170
Close To SOC Pin
close to SOC pin
182_0402_1%
182_0402_1%
1
1
2
R963
2
R964
@
DDRA_RCOMP
DDRB_RCOMP
+1.35V
@ESD@
2
DDR_CORE_PWROK
1
C1159
22P_0402_50V8J
+DDRA_SOC_VREFCA
1
2
R980
4.7K_0402_1%
1
1
2
R974
4.7K_0402_1%
2
C1136
.1U_0402_16V7K
3700R1@
USOC1
3050R1@
USOC1
3150R1@
USOC1
3710R1@
USOC1
3060R1@
USOC1
+1.35V
1
2
R965
4.7K_0402_1%
1
+DDRA_SOC_VREFDQ
A
S IC A32 FH8066501715906 QJ4S
SA00008U640
3700R3@
USOC1
S IC A32 FH8066501715194 QJ4V
SA00008U540
3050R3@
USOC1
S IC A32 FH8066501715194 QJ4V
SA00008UA20
3150R3@
USOC1
S IC A32 FH8066501715194 QK0G
SA00009IE00
3160R1@
USOC1
S IC A32 FH8066501715194 QK0J
SA00009IJ10
1
2
R966
4.7K_0402_1%
2
C1132
.1U_0402_16V7K
A
Security Classification
S IC A32 FH8066501715906 QJ4S
SA00008U650
S IC A32 FH8066501715194 QJ4V
SA00008U550
S IC A32 FH8066501715194 QJ4V
SA00008UA20
Compal Secret Data
2014/08/21
Deciphered Date
2015/08/21
Title
Compal Electronics, Inc.
S IC A32 FH8066501715194 QK0K
SA00009IK10
Issued Date
VLV-M SOC Memory DDR3L
Thursday, January 07, 2016
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-706P
Rev
0.1
Sheet
5
of
50
5
4
3
2

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