XXXX_ARMv7_thumb_instructions_set.pdf

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11
5
THUMB Instruction Set
This chapter describes the THUMB instruction set.
Format Summary
Opcode Summary
Format 1: move shifted register
Format 2: add/subtract
Format 3: move/compare/add/subtract immediate
Format 4: ALU operations
Format 5: Hi register operations/branch exchange
Format 6: PC-relative load
Format 7: load/store with register offset
Format 8: load/store sign-extended byte/halfword
Format 9: load/store with immediate offset
Format 10: load/store halfword
Format 11: SP-relative load/store
Format 12: load address
Format 13: add offset to Stack Pointer
Format 14: push/pop registers
Format 15: multiple load/store
Format 16: conditional branch
Format 17: software interrupt
Format 18: unconditional branch
Format 19: long branch with link
Instruction Set Examples
5-2
5-3
5-5
5-7
5-9
5-11
5-13
5-16
5-18
5-20
5-22
5-24
5-26
5-28
5-30
5-32
5-34
5-36
5-38
5-39
5-40
5-42
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
ARM7TDMI Data Sheet
ARM DDI 0029E
5-1
Open Access
THUMB Instruction Set
Format Summary
The THUMB instruction set formats are shown in the following gure.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
15
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
14
0
0
1
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
1
13
Op
1
Op
0
0
0
1
1
B
0
1
0
0
1
L
H
L
L
L
B
S
0
1
1
I
Offset5
Op Rn/offset3
Rd
Op
Op
Rd
0
1
Ro
Ro
Offset5
Offset5
Rd
Rd
0
1
0
0
Rb
Cond
1
0
1
1
1
0
R
S
H1 H2
Rs
Rs
Offset8
Rs
Rs/Hs
Word8
Rb
Rb
Rb
Rb
Word8
Word8
SWord7
Rlist
Rlist
Soffset8
Value8
Offset11
Offset
Rd
Rd
Move shifted register
Add/subtract
Move/compare/add
/subtract immediate
Rd
Rd/Hd
ALU operations
Hi register operations
/branch exchange
PC-relative load
Rd
Rd
Rd
Rd
Load/store with register
offset
Load/store sign-extended
byte/halfword
Load/store with immediate
offset
Load/store halfword
SP-relative load/store
Load address
Add offset to stack pointer
Push/pop registers
Multiple load/store
Conditional branch
Software Interrupt
Unconditional branch
Long branch with link
Open Access
9
10
11
12
13
14
15
16
17
18
19
0 SP
1
1
0
1
1
0
1
12
0
L
L
H
11
10
9
8
7
6
5
4
3
2
1
0
Figure 5-1: THUMB instruction set formats
5-2
ARM7TDMI Data Sheet
ARM DDI 0029E
THUMB Instruction Set
Opcode Summary
The following table summarizes the THUMB instruction set. For further
information about a particular instruction please refer to the sections listed in the
right-most column.
Mnemonic
ADC
ADD
AND
ASR
B
B
xx
BIC
BL
BX
CMN
CMP
EOR
LDMIA
LDR
LDRB
LDRH
LSL
LDSB
LDSH
LSR
MOV
MUL
MVN
Instruction
Add with Carry
Add
AND
Arithmetic Shift Right
Unconditional branch
Conditional branch
Bit Clear
Branch and Link
Branch and Exchange
Compare Negative
Compare
EOR
Load multiple
Load word
Load byte
Load halfword
Logical Shift Left
Load sign-extended
byte
Load sign-extended
halfword
Logical Shift Right
Move register
Multiply
Move Negative register
Lo register
operand
Hi register
operand
Condition
codes set
See Section:
5.4
5.1.3, 5.5, 5.12, 5.13
5.4
5.1, 5.4
5.16
5.17
5.4
5.5
5.4
5.3, 5.4, 5.5
5.4
5.15
5.7, 5.6, 5.9, 5.11
5.7, 5.9
5.8, 5.10
5.1, 5.4
5.8
5.8
5.1, 5.4
5.3, 5.5
5.4
5.4
Table 5-1: THUMB instruction set opcodes
ARM7TDMI Data Sheet
ARM DDI 0029E
5-3
Open Access
5.19
THUMB Instruction Set
Mnemonic
NEG
ORR
POP
PUSH
ROR
SBC
STMIA
STR
STRB
STRH
SWI
SUB
Instruction
Negate
OR
Pop registers
Push registers
Rotate Right
Subtract with Carry
Store Multiple
Store word
Store byte
Store halfword
Software Interrupt
Subtract
Test bits
Lo register
operand
Hi register
operand
Condition
codes set
See Section:
5.4
5.4
5.14
5.14
5.4
5.4
5.15
5.7, 5.9, 5.11
5.7
5.8, 5.10
5.17
5.1.3, 5.3
5.4
Open Access
TST
Table 5-1: THUMB instruction set opcodes (Continued)
The condition codes are unaffected by the format 5, 12 and 13
versions of this instruction.
The condition codes are unaffected by the format 5 version of this
instruction.
5-4
ARM7TDMI Data Sheet
ARM DDI 0029E
THUMB Instruction Set
5.1
Format 1: move shifted register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
Op
Offset5
Rs
Rd
Destination register
Source register
Immediate value
Opcode
Figure 5-2: Format 1
5.1.1 Operation
These instructions move a shifted value between Lo registers. The THUMB assembler
syntax is shown in
·
Table 5-2: Summary of format 1 instructions
.
Note
OP
00
01
All instructions in this group set the CPSR condition codes.
ARM equivalent
MOVS Rd, Rs, LSL #Offset5
MOVS Rd, Rs, LSR #Offset5
Action
Shift Rs left by a 5-bit immediate value
and store the result in Rd.
Perform logical shift right on Rs by a 5-
bit immediate value and store the result
in Rd.
Perform arithmetic shift right on Rs by a
5-bit immediate value and store the
result in Rd.
THUMB assembler
LSL Rd, Rs, #Offset5
LSR Rd, Rs, #Offset5
10
ASR Rd, Rs, #Offset5
MOVS Rd, Rs, ASR #Offset5
Table 5-2: Summary of format 1 instructions
ARM7TDMI Data Sheet
ARM DDI 0029E
5-5
Open Access
0 - LSL
1 - LSR
2 - ASR

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