0117-0257-10_K105-D_Logic_Analyzer_Addendum_68000_Disassembler_Feb84.pdf

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Publication Number 0117-0257-10
Release 1.0
February 1984
Kl05-D LOGIC ANALYZER
USERS MANUAL ADDENDUM
68000 DISASSEMBLER
Gould Inc., Design
&
Tes~
Systems Division
4600 Old Ironsides Drive
Santa Clara, CA 95050-1279
Telephone: (408) 988-6800
TWX/TELEX
#
910-338-0509
Copyright
©
1984. No part
of this publication may
be
reproduced without written
permission from Gou!d
!nCej
Design and Test Systems
Division. Printed in U.S.A.
P-2/84
CONTENTS
f'h:::lln+o ....
....."."'"'..,.
"'.
Page
INTRODUCTION
INTRODUCTION • • • • • • •
LOADING THE DISASSEMBLER
2
3
4
Figure
1-1
1-2
3-i
...
.
.
.
.
...
• • • • • • 1-1
• • • • • 1-7
SPECIFICATIONS
PHYSICAL DIMENSIONS AND WEIGHT • • • • • • • • • • • • • • • • 2-1
DISPLAYS
SCREEN DISPLAYS OF PREPROGRAMMED SET UP MENUS • • • • • • • • 3-1
INSTRUCTION SET
68000 INSTRUCTION SET • • • • • • • • • • • • • • • • • • • • 4-1
68000 Microprocessor Pinout Diagram. • • • • • • • • • • •
•
Typi
ca I RTE to Target System Connection • • •
• •••••••
Oi sassemb;er Data Format Set Up Menu. • • • • • • • • •
• ••
Clock Set Up Menu • • • • • • • • • • • • • • • • • • • • • • • •
Trace Contro I Set Up Menu • • • • • • •
• • • • • • • • • •
Captured Data in Disassembled Format • • • • • • • • • • • • • • •
Expanded , nstruction. • • • • • • • • •
• •••••••••
1-1
1-5
3-1
3-2
3-3
3-4
3-6
3-2
3-3
3-4
3-5
iif
Chap"ter 1
I NTROOLCT I ON
I NTROOOCT ION
This addendum provides the user with specific information on the 68000 target
microprocessor Disassembler. Included in the addendum are a microprocessor
pinout diagram, microprocessor-to-Iogic analyzer connection data, screen
displays of the preprogrammed menus, a screen display of captured data in the
disassembled format and special notes on the disassembler/logic analyzer.
04
03
02
01
00
AS
UDS
1
2
3
4
5
6
7
0
0
•
64
63
62
61
60
59
58
05
06
07
08
09
010
011
-
LDS
57
56
55
54
53
52
51
50
Oi2
R/W
OTACK
BG
BGACK
BR
--
9
10
11
12
13
vCC 14
ClK 15
GNO 16
HALT
17
RESET 18
VMA 19
E 20
VPA 21
BERR 22
IPl2 23
IPL1 24
IPlO 25
FC2 26
FC1 27
FCO 28
A1
29
A2 30
A3 31
A4 32
013
014
015
GNO
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
68000
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
--
0257-1-1
Figure 1-1.
68000 Microprocessor Pinout 0 i agram
1-1
I NTRODUCT ION
Table 1-1.
Microprocessor-To-logic Analyzer Connection Data
68000
SIGNAL
04
03
02
01
DO
AS
UOS
lOS
R/W
OTACK
BG
BGACK
BR
Yvv
68000
PIN
1
2'-
3
4
5
6
7
8
9
10
11
12
13
..
K105-0
PIN
ASSIGNMENT
A4
A3
A2
A1
AO
BJ
BO
CF
CE
-
-
ClK
GNO
HALT
RESET
VMA
E
VPA
BERR
IPl2
IPl1
IPlO
FC2
FC1
FCO
A1
A2
A3
A4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BK
GNO-A-B-C-O SECT IONS
CO
CC
CB
CA
C9
C8
B1
B2
B3
B4
1-2
I NTfO)l£TION
Tabie
i-i.
Microprocessor-Io-Logic Anaiyzer Connection Data (Cont'd)
68000
SIGNAL
D5
D6
D7
D8
D9
Dl0
D11
D12
D13
D14
D15
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
All
Al0
A9
A8
A7
A6
A5
68000
PIN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Kl05-D
PIN
ASSIGNMENT
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
GND-A-B-C-D SECTIONS
C7
C6
C5
C4
C3
C2
Cl
CO
BF
BE
BD
BC
BB
BA
B9
B8
B7
B6
B5
1-3

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